User:Pdp11.caps11

Instruction set

The three high-order bits of the 8-bit instruction word (labeled bits 0 through 2) are the operation code. For the six operations that refer to memory, bits 4 through 7 provide a 4-bit address. Bit 3 specifies indirection; if set, the address obtained as described so far points to an 8-bit value in memory that gives the actual effective address for the instruction. (The JMP instruction does not operate on a memory word, except if indirection is specified, but has the same bit fields.)

0		2	3	4				7
Operation			I	Offset

Memory pages

This use of the instruction word divides the 256-word memory into 16-word pages.

The standard assembler places constant values for arithmetic in the current page. Likewise, cross-page jumps and subroutine calls use an indirect address in the current page.

It was important to write routines to fit within 128-word pages, or to arrange routines to minimize page transitions, as references and jumps outside the current page required an extra word. Consequently, much time was spent cleverly conserving one or several words. Programmers deliberately placed code at the end of a page to achieve a free transition to the next page as PC was incremented.

Basic instructions

000 - AND - AND the memory operand with AC.

001 - TAD - Twos-complement ADd the memory operand to <L,AC> (a 13 bit value).

010 - ISZ - Increment the memory operand and Skip next instruction if result is Zero.

011 - DCA - Deposit AC into the memory operand and Clear AC.

100 - JMS - JuMp to Subroutine (storing return address in first word of subroutine!).

101 - JMP - JuMP.

110 - IOT - Input/Output Transfer (see below).

111 - OPR - microcoded OPeRations (see below).

IOT (Input-Output Transfer) instructions

The PDP-8 processor defined few of the IOT instructions, but simply provided a framework. Most IOT instructions were defined by the individual I/O devices.

0		2	3					8	9		11
6=IOT			Device						Function

Device

Bits 3 through 8 of an IOT instruction selected an I/O device. Some of these device addresses were standardized by convention:

00 was handled by the processor and not sent to any I/O device (see below)
01 was usually the high-speed paper tape reader
02 was the high-speed paper tape punch
03 was the console keyboard (and any associated low-speed paper tape reader)
04 was the console printer (and any associated low-speed paper tape punch)

Instructions for device 0 affected the processor as a whole. For example, ION (6001) enabled interrupt processing, and IOFF (6002) disabled it.

Function

Bits 9 through 11 of an IOT instruction selected the function(s) the device would perform. Simple devices (such as the paper tape reader and punch and the console keyboard and printer) would use the bits in standard ways:

Bit 11 caused the processor to skip the next instruction if the I/O device was ready
Bit 10 cleared AC
Bit 9 moved a word between AC and the device, initiated another I/O transfer, and cleared the device's "ready" flag

These operations took place in a well-defined order that gave useful results if more than one bit was set.

More complicated devices, such as disk drives, used these 3 bits in device-specific fashions. Typically, a device decoded the 3 bits to give 8 possible function codes.

OPR (OPeRate)

Many operations were achieved using OPR, including most of the conditionals. OPR does not address a memory location; conditional execution is achieved by conditionally skipping one instruction, which was typically a JMP.

The OPR instruction was said to be "microcoded." This did not mean what the word means today (that a lower-level program fetched and interpreted the OPR instruction), but meant that each bit of the instruction word specified a certain action, and the programmer could achieve several actions in a single instruction cycle by setting multiple bits. In use, a programmer would write several instruction mnemonics alongside one another, and the assembler would combine them with OR to devise the actual instruction word. Many I/O devices supported "microcoded" IOT instructions.

Microcoded actions took place in a well-defined sequence designed to maximize the utility of many combinations.

The OPR instructions came in Groups. Certain bits identified the Group of an OPR instruction, so it was impossible to combine the microcoded actions from different groups.

Group 1: CLA - clear AC; CLL - clear the L bit; CMA - ones complement AC; CML - complement L bit; IAC - increment <L,AC>; RAR - rotate <L,AC> right; RAL - rotate <L,AC> left; RTR - rotate <L,AC> right twice; RTL - rotate <L,AC> left twice

In most cases, the operations are sequenced so that they can be combined in the most useful ways. For example, combining CLA (CLear Accumulator), CLL (CLear Link), and IAC (Increment ACcumulator) first clears the AC and Link, then increments the accumulator, leaving it set to 1. Adding RAL to the mix (so CLA CLL IAC RAL) causes the accumulator to be cleared, incremented, then rotated left, leaving it set to 2. In this way, small integer constants were placed in the accumulator with a single instruction.

The combination CMA IAC, which the assembler let you abbreviate as CIA, produced the arithmetic inverse of AC: the twos-complement negation. Since there was no subtraction instruction, only the twos-complement add (TAD), computing the difference of two operands required first negating the subtrahend.

A Group 1 OPR instruction that has none of the microprogrammed bits set performs no action. The programmer can write NOP (No Operation) to assemble such an instruction.

Group 2: SMA - skip on AC < 0 (or group); SZA - skip on AC = 0 (or group); SNL - skip on L ≠ 0 (or group); SKP - skip unconditionally; SPA - skip on AC ≥ 0 (and group); SNA - skip on AC ≠ 0 (and group); SZL - skip on L = 0 (and group); CLA - clear AC; OSR - logically 'or' front-panel switches with AC; HLT - halt

A Group 2 OPR instruction that has none of the microprogrammed bits set is another No-Op instruction.

Group 3

Unused bit combinations of OPR were defined as a third Group of microprogrammed actions mostly affecting the MQ (Multiplier/Quotient) register.